architecture entries

16 bit32-bit application3DNow!
3DNow! Professional64-bitAdaline
address spaceANSI/SPARC Architecturearchitecture
arrayasynchronousasynchronous logic
Axiomatic Architecture Description LanguageBasic Object Adapterbig-endian
bit sliceBLOBbus
bus masterByzantineCA
Cache On A STickCAMcellular multiprocessing
Cellular Neural Networkcentral processing unitcloud computing
clusterCNNcognitive architecture
control buscontrol unitcoprocessor
Core Protocol StackDAGData Address Generator
data busdata feeddata flow
data pathdelayed control-transferdirect mapped cache
Direct Memory Accessdistributed memoryDNA computing
Dynamic Address Translationdynamic translationemulation
endianESAExtended Industry-Standard Architecture
faultfault tolerancefetch-execute cycle
first generationfirst generation computerflat address space
Flynn's taxonomyfourth generation computerHarvard architecture
HCFhithit rate
hypervisorIA32Industry Standard Architecture
inputInstruction Address Registerinstruction prefetch
instruction registerinstruction schedulinginstruction set
instruction set architectureIntelligent Input/OutputISA
Java Virtual MachineJoint Test Action GroupLisp Machine
little-endianmain memoryMany Integrated Core Architecture
memory address spacememory mapped I/OMemory Type Range Registers
Micro Channel Architecturemicrologmicroprocessor
middle-endianMoore's Lawnanocomputer
netNext Program CounterNon-Uniform Memory Access
northbridgeNPCNUXI problem
orthogonal instruction setoutputoverflow bit
page inpage outPE
ping-pongpipelinepipeline break
PNPPortable Object AdapterPowerPC Platform
power save modepredictprepaging
primary cacheredundancyRedundant Array of Independent Disks
Redundant Array of Inexpensive ServersRichard P. FeynmanSAME
scalarsecond generationsecond generation computer
segmented address spacesequential processingserial
serial processorservice-oriented architectureset associative cache
single program/multiple dataSOAsouthbridge
SSE-2stack pointerstate
Streaming SIMD Extensionssuperscalarsystolic array
Task Control Blockthird generation computerthree-tier
Translation Look-aside BufferUSBVery Large Memory
Very Long Instruction Wordvictim cachevirtual
virtual addressVLMvon Neumann architecture
wait stateWeb Service Definition LanguageWindows Open Service Architecture
wintelworking memoryworking set
write-throughXT bus architecture 



Loading