instruction
machine instructionInstruction Address Register
(IAR) The IBM name for program counter.
The IAR can be accessed by way of a supervisor call in supervisor state, but cannot be directly addressed in problem state.Last updated: 1995-03-21
instructional technology
Design, development, use, management and evaluation of process and resources for learning.
Instructional technology aims to promote the application of validated, practical procedures in the design and delivery of instruction. It is often defined either in terms of media and other technology used (e.g. audiovisual media and equipment and computers), or in terms of a systematic process which encompasses instructional design, development, delivery and evaluation. ["Instructional Technology: The Definition and Domains of the Field", 1994, Barbara Seels and Rita Richey, Washington, D.C., Association for Educational Communications and Technology].Last updated: 2010-01-29
instruction mnemonic
A word or acronym used in assembly language to represent a binary machine instruction operation code. Different processors have different instruction sets and therefore use a different set of mnemonics to represent them.
E.g. ADD, B (branch), BLT (branch if less than), SVC, MOVE, LDR (load register).Last updated: 1997-02-18
instruction prefetch
A technique which attempts to minimise the time a processor spends waiting for machine instructions to be fetched from memory. Instructions following the one currently being executed are loaded into a prefetch queue when the processor's external bus is otherwise idle. If the processor executes a branch instruction or receives an interrupt then the queue must be flushed and reloaded from the new address.
Instruction prefetch is often combined with pipelining in an attempt to keep the pipeline busy. By 1995 most processors used prefetching, e.g. Motorola 680x0, Intel 80x86. [First processors using prefetch?]Last updated: 1998-03-29
instruction register
(IR) The part of a central processing unit (CPU) control unit that holds the machine instruction currently being executed. The CPU's fetch-execute cycle loads instructions from memory into the instruction register. The IR in turn drives the instruction decoding logic that determines what operation teh CPU should perform on what data.
Modern processors have an instruction pipeline to minimise the time the control unit is waiting for instructions and data to be fetched from memory. This may distrubute the job of the IR over several registers in the pipeline.Last updated: 2018-08-31
instruction scheduling
The compiler phase that orders instructions on a pipelined, superscalar, or VLIW architecture so as to maximise the number of function units operating in parallel and to minimise the time they spend waiting for each other.
Examples are filling a delay slot; interspersing floating-point instructions with integer instructions to keep both units operating; making adjacent instructions independent, e.g. one which writes a register and another which reads from it; separating memory writes to avoid filling the write buffer. Norman P. Jouppi and David W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Processors", Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 272--282, 1989. [The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]instruction set
The collection of machine language instructions that a particular processor understands.
The term is almost synonymous with "instruction set architecture" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate.Last updated: 1999-07-05
instruction set architecture
(ISA) The parts of a processor's design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation, such as number of superscalar functional units, cache size and cycle speed, are not part of the ISA.
The definition of SPARC, for example, carefully distinguishes between an implementation and a specification.Last updated: 1999-01-16
Instruction Set Processor
<language>
(ISP) A family of languages for describing the instruction sets of computers.
["Computer Structures: Readings and Examples", D.P. Siewiorek et al, McGraw-Hill 1982].Last updated: 1995-10-12
Nearby terms:
Institut National de Recherche en Informatique et Automatique ♦ instruction ♦ Instruction Address Register
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