The compiler phase that orders instructions on a pipelined, superscalar, or VLIW architecture so as to maximise the number of function units operating in parallel and to minimise the time they spend waiting for each other.Examples are filling a delay slot; interspersing floating-point instructions with integer instructions to keep both units operating; making adjacent instructions independent, e.g. one which writes a register and another which reads from it; separating memory writes to avoid filling the write buffer. Norman P. Jouppi and David W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Processors", Proceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 272--282, 1989. [The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]
The collection of machine language instructions that a particular processor understands.The term is almost synonymous with "instruction set architecture" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate.
Last updated: 1999-07-05
instruction set architecture
(ISA) The parts of a processor's design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation, such as number of superscalar functional units, cache size and cycle speed, are not part of the ISA.The definition of SPARC, for example, carefully distinguishes between an implementation and a specification.
Last updated: 1999-01-16
Instruction Set Processor
(ISP) A family of languages for describing the instruction sets of computers.["Computer Structures: Readings and Examples", D.P. Siewiorek et al, McGraw-Hill 1982].
Last updated: 1995-10-12
instruction register ♦ instruction scheduling ♦ instruction set
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