Scalable Processor ARChitecture
<computer>
(SPARC) An instruction set architecture designed by Sun Microsystems for their own use in 1985. Sun was a maker of 680x0-based Unix workstations. Research versions of RISC processors had promised a major step forward in speed but existing manufacturers were slow to introduce a RISC type processor, so Sun went ahead and developed its own, based on the University of California at Berkley's RISC I and RISC II 1980-2. In keeping with their open philosophy, they licenced it to other companies, rather than manufacture it themselves. The evolution and standardisation of SPARC is now directed by the non-profit consortium SPARC International, Inc.
SPARC was not the first RISC processor. The AMD 29000 came before it, as did the MIPS R2000 (based on Stanford's design) and Hewlett-Packard Precision Architecture CPU, among others. The SPARC design was radical at the time, even omitting multiple cycle multiply and divide instructions (like a few others), while most RISC CPUs are more conventional. SPARC implementations usually contain 128 or 144 registers, (CISC designs typically had 16 or less). At each time 32 registers are available - 8 are global, the rest are allocated in a "window" from a stack of registers. The window is moved 16 registers down the stack during a function call, so that the upper and lower 8 registers are shared between functions, to pass and return values, and 8 are local. The window is moved up on return, so registers are loaded or saved only at the top or bottom of the register stack. This allows functions to be called in as little as 1 cycle. Like some other RISC processors, reading global register zero always returns zero and writing it has no effect. SPARC is pipelined for performance, and like previous processors, a dedicated condition code register holds comparison results. SPARC is "scalable" mainly because the register stack can be expanded (up to 512, or 32 windows), to reduce loads and saves between functions, or scaled down to reduce interrupt or context switch time, when the entire register set has to be saved. Function calls are usually much more frequent, so the large register set is usually a plus. SPARC is not a chip, but a specification, and so there are various implementations of it. It has undergone revisions, and now has multiply and divide instructions. Most versions are 32 bits, but there are designs for 64-bit and superscalar versions. SPARC was submitted to the IEEE society to be considered for the P1754 microprocessor standard. SPARC(R) is a registered trademark of SPARC International, Inc. in the United States and other countries. [The SPARC Architecture Manual, v8, ISBN 0-13-825001-4].Last updated: 1994-11-01
Nearby terms:
Scalable Coherent Interface ♦ Scalable Processor ARChitecture ♦ Scalable Sampling Rate
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