architecture

Related entries include:

16 bit; 32-bit application; 3DNow!; 3DNow! Professional; 64-bit; Adaline; address space; ANSI/SPARC Architecture; architecture; array; asynchronous; asynchronous logic; Axiomatic Architecture Description Language; Basic Object Adapter; big-endian; bit slice; BLOB; bus; bus master; Byzantine; CA; Cache On A STick; CAM; cellular multiprocessing; Cellular Neural Network; central processing unit; cloud computing; cluster; CNN; cognitive architecture; control bus; control unit; Core Protocol Stack; DAG; Data Address Generator; data bus; data feed; data flow; data path; direct mapped cache; Direct Memory Access; distributed memory; DNA computing; Dynamic Address Translation; dynamic translation; emulation; endian; ESA; Extended Industry-Standard Architecture; fault; fault tolerance; fetch-execute cycle; first generation; first generation computer; flat address space; Flynn's taxonomy; fourth generation computer; Harvard architecture; HCF; hit; hit rate; IA32; Industry Standard Architecture; input; Instruction Address Register; instruction prefetch; instruction set; instruction set architecture; Intelligent Input/Output; ISA; Java Virtual Machine; Lisp Machine; little-endian; main memory; memory address space; memory mapped I/O; Memory Type Range Registers; Micro Channel Architecture; microlog; microprocessor; middle-endian; Moore's Law; nanocomputer; net; Next Program Counter; Non-Uniform Memory Access; northbridge; NPC; NUXI problem; orthogonal instruction set; output; overflow bit; page in; page out; PE; ping-pong; pipeline; pipeline break; PNP; Portable Object Adapter; PowerPC Platform; power save mode; predict; prepaging; primary cache; redundancy; Redundant Array of Independent Disks; Redundant Array of Inexpensive Servers; Richard P. Feynman; SAME; scalar; second generation; second generation computer; segmented address space; sequential processing; serial; serial processor; service-oriented architecture; set associative cache; single program/multiple data; SOA; southbridge; SSE-2; stack pointer; state; Streaming SIMD Extensions; superscalar; systolic array; Task Control Block; third generation computer; three-tier; Translation Look-aside Buffer; USB; Very Large Memory; Very Long Instruction Word; victim cache; virtual; virtual address; VLM; von Neumann architecture; wait state; Web Service Definition Language; Windows Open Service Architecture; wintel; working memory; working set; write-through; XT bus architecture;