segmented address space

<architecture> An addressing scheme where all memory references are formed by adding an offset to a base address held in a segment register.

The effect is to segment memory into blocks, which may overlap either partially or completely, depending on the contents of the segment registers but normally they would be distinct to give access to the maximum total range of addresses. In this case the scheme does provide some degree of memory protection within a single process since, for example, a data reference cannot affect an area of memory containing code. However, compilers must either generate slower code or code with artificial limits on the size of data structures.

The best known implementation is that used on the Intel 8086 and later Intel microprocessors, where a 16-bit offset is added to a 16-bit base address held in one of four segment base registers. Each instruction has a default segment (code (CS), data (DS), stack (SS), ? (ES)) which determines which segment register is used. Special prefix instructions allow this default to be overridden.

Other computers, such as GE-645/Honeywell Multics, Burroughs large systems (B-5500, B-6600), and others, have used segmentation to good effect.

Opposite: flat address space. See also addressing mode.

[In what way were the others better than Intel's brain damaged implementation?].

Last updated: 2004-06-01

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Nearby terms: segmentation « segmentation and reassembly « segmentation fault « segmented address space » segv » SEI » Seiko RC-4000


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