(circuit design) A technique used to increase the controllability and observability of a logic circuit by incorporating "scan registers" into the circuit. Normally these act like flip-flops but they can be switched into a "test" mode where they all become one long shift register. This allows data to be clocked serially through all the scan registers and out of an output pin at the same time as new data is clocked in from an input pin.
Using this technique, the state of certain points in the circuit can be examined and modified at any time by suspending normal operation and switching to test mode. If the scan path is placed adjacent to the circuit's input and output pins then this is known as "boundary scan".
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Nearby terms: scan line « scanner « scanno « scan path » scan register » SCC » SCCS